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1 MX25V1006E datasheet p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
2 contents features .................................................................................................................................................................. 4 general ........... ............................................................................................................................................... 4 performance ........... .................................................................................................................................... 4 software features ................................................................................................................................... 4 hardware features ................................................................................................................................... 5 general description ......................................................................................................................................... 5 pin configurations .............................................................................................................................................. 6 8-land uson (2x3mm) ................................................................................................................................... 6 8-pin tssop (173mil) ........... ........................................................................................................................... 6 8-pin sop (150mil) ........................................................................................................................................... 6 pin description ...................................................................................................................................................... 6 block diagram ....................................................................................................................................................... 7 data protection .................................................................................................................................................... 8 table 1. protected area sizes ............................................................................................................................ 8 hold feature .......................................................................................................................................................... 9 figure 1. hold condition operation ................................................................................................................... 9 table 2. command definition ........... ........................................................................................................ 10 memory organization ....................................................................................................................................... 11 table 3. memory organization ........................................................................................................................ 11 device operation ................................................................................................................................................ 12 figure 2. serial modes supported .................................................................................................................... 12 command description ....................................................................................................................................... 13 (1) write enable (wren) ................................................................................................................................. 13 (2) write disable (wrdi) ............ ...................................................................................................................... 13 (3) read identifcation (rdid) .......................................................................................................................... 13 (4) read status register (rdsr) ........... ......................................................................................................... 14 status register ................................................................................................................................................. 14 (5) write status register (wrsr) ............ ........................................................................................................ 15 table 4. protection modes ................................................................................................................................ 15 (6) read data bytes (read) ........................................................................................................................... 16 (7) read data bytes at higher speed (fast_read) ..................................................................................... 16 (8) dual output mode (dread) ....................................................................................................................... 16 (9) sector erase (se) ....................................................................................................................................... 16 (10) block erase (be) ....................................................................................................................................... 17 (11) chip erase (ce) ........................................................................................................................................ 17 (12) page program (pp) ................................................................................................................................... 17 (13) deep power-down (dp) ............................................................................................................................ 18 (14) release from deep power-down (rdp), read electronic signature (res) ........................................... 18 (15) read electronic manufacturer id & device id (rems) ............................................................................ 19 table of id defnitions ...................................................................................................................................... 19 p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
3 power-on state ................................................................................................................................................... 20 electrical specifications .............................................................................................................................. 21 absolute maximum ratings ................................................................................................................... 21 capacitance ta = 25c, f = 1.0 mhz ........................................................................................................... 21 figure 5. input test waveforms and measurement level ............ ................................................ 22 figure 6. output loading ......................................................................................................................... 22 table 5. dc characteristics ................................................................................................................... 23 table 6. ac characteristics .................................................................................................................. 24 table 7. power-up timing ........... ..................................................................................................................... 25 initial delivery state ............................................................................................................................... 25 timing analysis ........................................................................................................................................................ 26 figure 7. serial input timing ............................................................................................................................ 26 figure 8. output timing .................................................................................................................................... 26 figure 9. hold timing ....................................................................................................................................... 27 figure 10. wp# disable setup and hold timing during wrsr when srwd=1 ........... .................................. 27 figure 11. write enable (wren) sequence (command 06) ........................................................................... 28 figure 12. write disable (wrdi) sequence (command 04) ............ ................................................................ 28 figure 13. read identifcation (rdid) sequence (command 9f) .................................................................... 28 figure 14. read status register (rdsr) sequence (command 05) ........... ................................................... 29 figure 15. write status register (wrsr) sequence (command 01) ............ ................................................. 29 figure 16. read data bytes (read) sequence (command 03) .................................................................... 29 figure 17. read at higher speed (fast_read) sequence (command 0b) ........... ..................................... 30 figure 18. dual output read mode sequence (command 3b) ....................................................................... 30 figure 19. page program (pp) sequence (command 02) .............................................................................. 31 figure 20. sector erase (se) sequence (command 20) ................................................................................ 32 figure 21. block erase (be) sequence (command 52 or d8) ........................................................................ 32 figure 22. chip erase (ce) sequence (command 60 or c7) ......................................................................... 33 figure 23. deep power-down (dp) sequence (command b9) ....................................................................... 33 figure 24. read electronic signature (res) sequence (command ab) ........................................................ 33 figure 25. release from deep power-down (rdp) sequence (command ab) ............................................. 34 figure 26. read electronic manufacturer & device id (rems) sequence (command 90) ............................ 34 figure 27. power-up timing ............................................................................................................................. 35 recommended operating conditions ......................................................................................................... 36 figure 28. ac timing at device power-up ....................................................................................................... 36 figure 29. power-down sequence .................................................................................................................. 37 erase and programming performance .................................................................................................... 38 data retention .................................................................................................................................................... 38 latch-up characteristics .............................................................................................................................. 38 ordering information ...................................................................................................................................... 39 part name description ..................................................................................................................................... 40 package information ........................................................................................................................................ 41 revision history ................................................................................................................................................. 44 p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
4 general ? serial peripheral interface compatible -- mode 0 and mode 3 ? 1,048,576 x 1 bit structure or 524,288 x 2 bits (dual output mode) structure ? 32 equal sectors with 4k byte each - any sector can be erased individually ? 2 equal blocks with 64k byte each - any block can be erased individually ? single power supply operation - 2.35 to 3.6 volt for read, erase, and program operations ? latch-up protected to 100ma from -1v to vcc +1v performance ? high performance - fast access time: 75mhz serial clock - serial clock of dual output mode: 70mhz - fast program time: 0.6ms(typ.) and 1ms(max.)/page (256-byte per page) - byte program time: 9us - fast erase time: 40ms(typ.)/sector (4k-byte per sector) ; 0.8s(typ.) and 2s(max.)/chip ? low power consumption - low active read current: 12ma(max.) at 75mhz and 4ma(max.) at 33mhz - low active programming current: 15ma (typ.) - low active sector erase current: 9ma (typ.) - low standby current: 15ua (typ.) - deep power-down mode 2ua (typ.) ? minimum 100,000 erase/program cycles ? 20 years data retention software features ? input data format - 1-byte command code ? block lock protection - the bp0~bp1 status bit defnes the size of the area to be software protected against program and erase in - structions. ? auto erase and auto program algorithm - automatically erases and verifes data at selected sector - automatically programs and verifes data at selected page by an internal algorithm that automatically times the program pulse widths (any page to be programed should have page in the erased state frst) ? status register feature ? electronic identifcation - jedec 2-byte device id - res command, 1-byte device id 1m-bit [x 1/x 2] cmos serial flash features p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
5 hardware features ? sclk input - serial clock input ? si/sio0 - serial data input or serial data output for dual output mode ? so/sio1 - serial data output or serial data output for dual output mode ? wp# pin - hardware write protection ? hold# pin - pause the chip without diselecting the chip ? package - 8-uson (2x3mm) - 8-pin tssop (173mil) - 8-pin sop (150mil) - all devices are rohs compliant and halogen-free general description MX25V1006E is a cmos 1,048,576 bit serial flash memory, which is confgured as 131,072 x 8 internally. MX25V1006E features a serial peripheral interface and software protocol allowing operation on a simple 3-wire bus. the three bus signals are a clock input (sclk), a serial data input (si), and a serial data output (so). serial access to the device is enabled by cs# input. MX25V1006E provides sequential read operation on whole chip. after program/erase command is issued, auto program/erase algorithms which program/erase and verify the speci - fed page or sector/block locations will be executed. program command is executed on page (256 bytes) basis, and erase command is executes on chip or sector (4k-bytes) or block (64k-bytes). to provide user with ease of interface, a status register is included to indicate the status of the chip. the status read command can be issued to detect completion status of a program or erase operation via wip bit. when the device is not in operation and cs# is high, it is put in standby mode. the MX25V1006E utilizes macronix's proprietary memory cell, which reliably stores memory contents even after 100,000 program and erase cycles. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
6 pin configurations symbol description cs# chip select si/sio0 serial data input (for 1 x i/o)/ serial data input & output (for dual output mode) so/sio1 serial data output (for 1 x i/o)/ serial data input & output (for dual output mode) sclk clock input hold# hold, to pause the device without deselecting the device wp# write protection vcc + 3.3v power supply gnd ground pin description 8-land uson (2x3mm) 1 2 3 4 cs# so/sio1 wp# gnd 8 7 6 5 vcc hold# sclk si/sio0 8-pin tssop (173mil) 1 2 3 4 cs# so/sio1 wp# gnd vcc hold# sclk si/sio0 8 7 6 5 8-pin sop (150mil) 1 2 3 4 cs# so/sio1 wp# gnd vcc hold# sclk si/sio0 8 7 6 5 p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
7 block diagram address generator memory array page buffer y-decoder x-decoder data register sram buffer si/sio0 sclk clock generator state machine mode logic sense amplifier hv generator output buffer so/sio1 cs#, wp#, hold# p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
8 data protection during power transition, there may be some false system level signals which result in inadvertent erasure or programming. the device is designed to protect itself from these accidental write cycles. the state machine will be reset as standby mode automatically during power up. in addition, the control register architecture of the device constrains that the memory contents can only be changed after specifc command sequences have completed successfully. in the following, there are several features to protect the system from the accidental write cycles during vcc power- up and power-down or from system noise. ? valid command length checking: the command length will be checked whether it is at byte base and com - pleted on byte boundary. ? write enable (wren) command: wren command is required to set the write enable latch bit (wel) before other command to change data. the wel bit will return to reset stage under following situation: - power-up - w rite disable (wrdi) command completion - w rite status register (wrsr) command completion - page program (pp) command completion - sector erase (se) command completion - block erase (be) command completion - chip erase (ce) comma nd completion ? software protection mode (spm): by using bp0-bp1 bits to set the part of flash protected from data change. ? hardware protection mode (hpm): by using wp# going low to protect the bp0-bp1 bits and srwd bit from data change. ? deep power down mode: by entering deep power down mode, the fash device also is under protected from writing all commands except release from deep power-down mode command (rdp) and read electronic sig - nature command (res). table 1. protected area sizes status bit protect level 1mb bp1 bp0 0 0 0 (none) none 0 1 1 (1 block) block 1 1 0 2 (2 blocks) all 1 1 3 (all) all p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
9 hold feature hold# pin signal goes low to hold any serial communications with the device. the hold feature will not stop the operation of write status register, programming, or erasing in progress. the operation of hold requires chip select(cs#) keeping low and starts on falling edge of hold# pin signal while serial clock (sclk) signal is being low (if serial clock signal is not being low, hold operation will not start until serial clock signal being low). the hold condition ends on the rising edge of hold# pin signal while se - rial clock(sclk) signal is being low(if serial clock signal is not being low, hold operation will not end until serial clock being low), see figure 1. the serial data output (so) is high impedance, both serial data input (si) and serial clock (sclk) are don't care during the hold operation. if chip select (cs#) drives high during hold operation, it will reset the internal logic of the device. to re-start communication with chip, the hold# must be at high and cs# must be at low. hold# cs# sclk hold condition (standard) hold condition (non-standard) figure 1. hold condition operation p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
10 table 2. command definition (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst. (2) it is not recommended to adopt any other code which is not in the command defnition table above. command (byte) wren (write enable) wrdi (write disable) rdid (read identifcation) rdsr (read status register) wrsr (write status register) read (read data) 1st 06 (hex) 04 (hex) 9f (hex) 05 (hex) 01 (hex) 03 (hex) 2nd ad1 3rd ad2 4th ad3 5th action sets the (wel) write enable latch bit resets the (wel) write enable latch bit outputs manufacturer id and 2-byte device id to read out the status register to write new values to the status register n bytes read out until cs# goes high command (byte) fast read (fast read data) dread (dual output mode) se (sector erase) be (block erase) ce (chip erase) pp (page program) 1st 0b (hex) 3b (hex) 20 (hex) 52 or d8 (hex) 60 or c7 (hex) 02 (hex) 2nd ad1 ad1 ad1 ad1 ad1 3rd ad2 ad2 ad2 ad2 ad2 4th ad3 ad3 ad3 ad3 ad3 5th x action n bytes read out until cs# goes high n bytes read out until cs# goes high to erase the selected sector to erase the selected block to erase the whole chip to program the selected page command (byte) dp (deep power- down) rdp (release from deep power- down) res (read electronic id) rems (read electronic manufacturer & device id) 1st b9 (hex) ab (hex) ab (hex) 90 (hex) 2nd x x 3rd x x 4th x add(1) 5th action enters deep power down mode release from deep power down mode to read out 1-byte device id output the manufacturer id and device id p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
11 table 3. memory organization block sector address range 1 31 01f000h 01ffffh : : : 16 010000h 010fffh 0 15 00f000h 00ffffh : : : 3 003000h 003fffh 2 002000h 002fffh 1 001000h 001fffh 0 000000h 000fffh memory organization p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
12 device operation 1. before a command is issued, status register should be checked to ensure the device is ready for the intended operation. 2. when incorrect command is inputted to this lsi, this lsi becomes standby mode and keeps the standby mode until next cs# falling edge. in standby mode, so pin of this lsi should be high-z. the cs# falling time needs to follow tchcl spec. (please refer to table 6. ac characteristics) 3. when correct command is inputted to this lsi, this lsi becomes active mode and keeps the active mode until next cs# rising edge. the cs# rising time needs to follow tclch spec. (please refer to table 6. ac character - istics) 4. input data is latched on the rising edge of serial clock(sclk) and data shifts out on the falling edge of sclk. the difference of serial mode 0 and mode 3 is shown as figure 2. 5. for the following instructions: rdid, rdsr, read, f ast_read, dread, res and rems the shifted-in in - struction sequence is followed by a data-out sequence. after any bit of data being shifted out, the cs# can be high. for the following instructions: wren, wrdi, wrsr, se, be, ce, pp, rdp and dp the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. 6. during the progress of w rite status register, program, erase operation, to access the memory array is neglect - ed and not affect the current operation of write status register, program, and erase. figure 2. serial modes supported sclk msb cpha shift in shift out si 0 1 cpol 0 (serial mode 0) (serial mode 3) 1 so sclk msb note: cpol indicates clock polarity of serial master: -cpol=1 for sclk high while idle, -cpol=0 for sclk low while not transmitting. cpha indicates clock phase. the combination of cpol bit and cpha bit decides which serial mode is supported. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
13 command description (1) write enable (wren) the write enable (wren) instruction is for setting write enable latch (wel) bit. for those instructions like pp, se, be, ce, and wrsr, which are intended to change the device content, should be set every time after the wren in - struction setting the wel bit. the sequence of issuing wren instruction is: cs# goes low send ing wren instruction code cs# goes high. (see figure 11 ) (2) write disable (wrdi) the write disable (wrdi) instruction is for resetting write enable latch (wel) bit. the sequence of issuing wrdi instruction is: cs# goes low send ing wrdi instruction code cs# goes high. (see figure 12 ) the wel bit is reset by following situations: - power-up - w rite disable (wrdi) instruction completion - w rite status register (wrsr) instruction completion - page program (pp) instruction completion - sector erase (se) instruction completion - block erase (be) instruction completion - chip erase (ce) instruction completion (3) read identifcation (rdid) the rdid instruction is for reading the manufacturer id of 1-byte and followed by device id of 2-byte. the macronix manufacturer id and device id are listed as 7deohri ,''hqlwlrqv . the sequence of issuing rdid instruction is: cs# goes lowsending rdid instruction code24-bits id data out on soto end rdid operation can use cs# to high at any time during data out. (see figure. 13) while program/erase operation is in progress, it will not decode the rdid instruction, so there's no effect on the cy - cle of program/erase operation which is currently in progress. when cs# goes high, the device is at standby stage. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
14 (4) read status register (rdsr) the rdsr instruction is for reading status register bits. the read status register can be read at any time (even in program/erase/write status register condition) and continuously. it is recommended to check the write in progress (wip) bit before sending a new instruction when a program, erase, or write status register operation is in progress. the sequence of issuing rdsr instruction is: cs# goes lowsending rdsr instruction codestatus register data out on so (see figure. 14) the defnition of the status register bits is as below: wip bit. the write in progress (wip) bit, a volatile bit, indicates whether the device is busy in program/erase/write status register progress. when wip bit sets to 1, which means the device is busy in program/erase/write status register progress. when wip bit sets to 0, which means the device is not in progress of program/erase/write status register cycle. wel bit. the write enable latch (wel) bit, a volatile bit, indicates whether the device is set to internal write enable latch. when wel bit sets to 1, which means the internal write enable latch is set, the device can accept program/ erase/write status register instruction. when wel bit sets to 0, which means no internal write enable latch; the de - vice will not accept program/erase/write status register instruction. bp1, bp0 bits. the block protect (bp1, bp0) bits, non-volatile bits, indicate the protected area (as defned in table 1 ) of the device to against the program/erase instruction without hardware protection mode being set. to write the block protect (bp1, bp0) bits requires the write status register (wrsr) instruction to be executed. those bits defne the protected area of the memory to against page program (pp), sector erase (se), block erase (be) and chip erase(ce) instructions (only if all block protect bits set to 0, the ce instruction can be executed) srwd bit. the status register write disable (srwd) bit, non-volatile bit, is operated together with write protec - tion (wp#) pin for providing hardware protection mode. the hardware protection mode requires srwd sets to 1 and wp# pin signal is low stage. in the hardware protection mode, the write status register (wrsr) instruction is no longer accepted for execution and the srwd bit and block protect bits (bp1, bp0) are read only. notes: 1. see the table " protected area sizes". bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 srwd (status register write protect) 0 0 0 bp1 (level of protected block) bp0 (level of protected block) wel (write enable latch) wip (write in progress bit) 1=status register write disable (note 1) (note 1) 1=write enable 0=not write enable 1=write operation 0=not in write operation status register p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
15 (5) write status register (wrsr) the wrsr instruction is for changing the values of status register bits. before sending wrsr instruction, the write enable (wren) instruction must be decoded and executed to set the write enable latch (wel) bit in ad - vance. the wrsr instruction can change the value of block protect (bp1, bp0) bits to defne the protected area of memory (as shown in table 1 ). the wrsr also can set or reset the status register write disable (srwd) bit in accordance with write protection (wp#) pin signal. the wrsr instruction cannot be executed once the hardware protected mode (hpm) is entered. the sequence of issuing wrsr instruction is: cs# goes low sending wrsr instruction code status register data on si cs# goes high. (see figure 15 ) the wrsr instruction has no effect on b6, b5, b4, b1, b0 of the status register. the cs# must go high exactly at the byte boundary; otherwise, the instruction will be rejected and not executed. the self-timed write status register cycle time (tw) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the write status register cycle is in progress. the wip sets 1 during the tw timing, and sets 0 when write status register cycle is completed, and the write enable latch (wel) bit is reset. table 4. protection modes note: 1. as defned by the values in the block protect (bp1, bp0) bits of the status register, as shown in table 1. as the table above showing, the summary of the software protected mode (spm) and hardware protected mode (hpm). software protected mode (spm): - when sr wd bit=0, no matter wp# is low or high, the wren instruction may set the wel bit and can change the values of srwd, bp1, bp0. the protected area, which is defned by bp1, bp0, is at software protected mode (spm). - when sr wd bit=1 and wp# is high, the wren instruction may set the wel bit can change the values of srwd, bp1, bp0. the protected area, which is defned by bp1, bp0, is at software protected mode (spm) note: if srwd bit=1 but wp# is low, it is impossible to write the status register even if the wel bit has previ - ously been set. it is rejected to write the status register and not be executed. hardware protected mode (hpm): - when sr wd bit=1, and then wp# is low (or wp# is low before srwd bit=1), it enters the hardware pro - tected mode (hpm). the data of the protected area is protected by software protected mode by bp1, bp0 and hardware protected mode by the wp# to against data modifcation. note: to exit the hardware protected mode, it requires wp# driving high once the hardware protected mode is entered. if the wp# pin is permanently connected to high, the hardware protected mode can never be en - tered; only can use software protected mode via bp1, bp0. mode status register condition wp# and srwd bit status memory software protection mode (spm) status register can be written in (wel bit is set to "1") and the srwd, bp0-bp1 bits can be changed. wp#=1 and srwd bit=0, or wp#=0 and srwd bit=0, or wp#=1 and srwd=1 the protected area cannot be programmed or erased. hardware protection mode (hpm) the srwd, bp0-bp1 of status register bits cannot be changed. wp#=0, srwd bit=1 the protected area cannot be programmed or erased. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
16 (6) read data bytes (read) the read instruction is for reading data out. the address is latched on rising edge of sclk, and data shifts out on the falling edge of sclk at a maximum frequency fr. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing read instruction is: cs# goes low sending read instruction code 3-byte address on si data out on so to end read operation can use cs# to high at any time during data out. (see figure. 16) (7) read data bytes at higher speed (fast_read) the fast_read instruction is for quickly reading data out. the address is latched on rising edge of sclk, and data of each bit shifts out on the falling edge of sclk at a maximum frequency fc. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single fast_read instruction. the address counter rolls over to 0 when the highest address has been reached. the sequence of issuing fast_read instruction is: cs# goes low sending fast_read instruction code 3-byte address on si 1-dummy byte address on sidata out on so to end fast_read operation can use cs# to high at any time during data out. (see figure. 17) while program/erase/write status register cycle is in progress, fast_read instruction is rejected without any im - pact on the program/erase/write status register current cycle. (8) dual output mode (dread) the dread instruction enable double throughput of serial flash in read mode. the address is latched on rising edge of sclk, and data of every two bits(interleave on 1i/2o pins) shift out on the falling edge of sclk at a maxi - mum frequency ft. the frst address byte can be at any location. the address is automatically increased to the next higher address after each byte data is shifted out, so the whole memory can be read out at a single dread instruc - tion. the address counter rolls over to 0 when the highest address has been reached. once writing dread instruc - tion, the following data out will perform as 2-bit instead of previous 1-bit. the sequence is shown as figure 18 . while program/erase/write status register cycle is in progress, dread instruction is rejected without any impact on the program/erase/write status register current cycle. the dread only performs read operation. program/erase /read id/read status....operations do not support dread throughputs. (9) sector erase (se) the sector erase (se) instruction is for erasing the data of the chosen sector to be "1". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit before sending the sector erase (se). any address of the sector (see table 3 ) is a valid address for sector erase (se) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
17 address bits [am-a12] (am is the most signifcant address) select the sector address. the sequence of issuing se instruction is: cs# goes low sending se instruction code 3-byte address on si cs# goes high. (see figure 20 ) the self-timed sector erase cycle time (tse) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be checked out during the sector erase cycle is in progress. the wip sets 1 during the tse timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp1, bp0 bits, the sector erase (se) instruction will not be executed on the page. (10) block erase (be) the block erase (be) instruction is for erasing the data of the chosen block to be "1". a write enable (wren) in - struction must execute to set the write enable latch (wel) bit before sending the block erase (be). any address of the block (see table 3 ) is a valid address for block erase (be) instruction. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not executed. the sequence of issuing be instruction is: cs# goes low sending be instruction code 3-byte address on si cs# goes high. (see figure 21 ) the self-timed block erase cycle time (tbe) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the sector erase cycle is in progress. the wip sets 1 during the tbe timing, and sets 0 when sector erase cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp1, bp0 bits, the block erase (be) instruction will not be executed on the page. (11) chip erase (ce) the chip erase (ce) instruction is for erasing the data of the whole chip to be "1". a write enable (wren) instruc - tion must execute to set the write enable latch (wel) bit before sending the chip erase (ce). any address of the sector (see table 3 ) is a valid address for chip erase (ce) instruction. the cs# must go high exactly at the byte boundary( the latest eighth of address byte been latched-in); otherwise, the instruction will be rejected and not ex - ecuted. the sequence of issuing ce instruction is: cs# goes low sending ce instruction code cs# goes high. (see figure 22 ) the self-timed chip erase cycle time (tce) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the chip erase cycle is in progress. the wip sets 1 during the tce timing, and sets 0 when chip erase cycle is completed, and the write enable latch (wel) bit is reset. if the chip is protected by bp1, bp0 bits, the chip erase (ce) instruction will not be executed. it will be only executed when bp1, bp0 all set to "0". (12) page program (pp) the page program (pp) instruction is for programming the memory to be "0". a write enable (wren) instruction must execute to set the write enable latch (wel) bit before sending the page program (pp). the last address byte (the 8 least signifcant address bits, a7-a0) should be set to 0 for 256 bytes page program. if a7-a0 are not all zero, transmitted data that exceed page length are programmed from the starting address (24-bit address that last 8 bit are all 0) of currently selected page. the cs# must keep during the whole page program cycle. the cs# must go high exactly at the byte boundary (the latest eighth of address byte been latched-in); otherwise, the instruc - p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
18 tion will be rejected and not executed. if the data bytes sent to the device exceeds 256, the last 256 data byte is programmed at the request page and previous data will be disregarded. if the data bytes sent to the device has not exceeded 256, the data will be programmed at the request address of the page. there will be no effort on the other data bytes of the same page. the sequence of issuing pp instruction is: cs# goes low sending pp instruction code 3-byte address on si at least 1-byte on data on si cs# goes high. (see figure 19 ) the self-timed page program cycle time (tpp) is initiated as soon as chip select (cs#) goes high. the write in progress (wip) bit still can be check out during the page program cycle is in progress. the wip sets 1 during the tpp timing, and sets 0 when page program cycle is completed, and the write enable latch (wel) bit is reset. if the page is protected by bp1, bp0 bits, the page program (pp) instruction will not be executed. (13) deep power-down (dp) the deep power-down (dp) instruction is for setting the device on the minimizing the power consumption (to enter - ing the deep power-down mode), the standby current is reduced from isb1 to isb2). the deep power-down mode requires the deep power-down (dp) instruction to enter, during the deep power-down mode, the device is not ac - tive and all write/program/erase instruction are ignored. when cs# goes high, it's only in standby mode not deep power-down mode. it's different from standby mode. the sequence of issuing dp instruction is: cs# goes low sending dp instruction code cs# goes high. (see fig- ure 23) once the dp instruction is set, all instruction will be ignored except the release from deep power-down mode (rdp) and read electronic signature (res) instruction. (res instruction to allow the id been read out). when power- down, the deep power-down mode automatically stops, and when power-up, the device automatically is in standby mode. for rdp instruction the cs# must go high exactly at the byte boundary (the latest eighth bit of instruction code been latched-in); otherwise, the instruction will not executed. as soon as chip select (cs#) goes high, a delay of tdp is required before entering the deep power-down mode and reducing the current to isb2. (14) release from deep power-down (rdp), read electronic signature (res) the release from deep power-down (rdp) instruction is terminated by driving chip select (cs#) high. when chip select (cs#) is driven high, the device is put in the stand-by power mode. if the device was not previously in the deep power-down mode, the transition to the stand-by power mode is immediate. if the device was previously in the deep power-down mode, though, the transition to the stand-by power mode is delayed by tres2, and chip select (cs#) must remain high for at least tres2(max), as specifed in table 6 . once in the stand-by power mode, the device waits to be selected, so that it can receive, decode and execute instructions. res instruction is for reading out the old style of 8-bit electronic signature, whose values are shown as table of id defnitions . this is not the same as rdid instruction. it is not recommended to use for new design. for new deisng, please use rdid instruction. even in deep power-down mode, the rdp and res are also allowed to be executed, only except the device is in progress of program/erase/write cycle; there's no effect on the current program/erase/ write cycle in progress. the sequence is shown as figure 24 and figure 25 . p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
19 table of id defnitions rdid command manufacturer id memory type memory density c2 20 11 res command electronic id 10 rems command manufacturer id device id c2 10 the res instruction is ended by cs# goes high after the id been read out at least once. the id outputs repeat - edly if continuously send the additional clock cycles on sclk while cs# is at low. if the device was not previously in deep power-down mode, the device transition to standby mode is immediate. if the device was previously in deep power-down mode, there's a delay of tres2 to transit to standby mode, and cs# must remain to high at least tres2(max). once in the standby mode, the device waits to be selected, so it can be received, be decoded, and be executed instruction. the rdp instruction is for releasing from deep power down mode. (15) read electronic manufacturer id & device id (rems) the rems instruction is an alternative to the release from power-down/device id instruction that provides both the jedec assigned manufacturer id and the specifc device id. the rems instruction is very similar to the release from power-down/device id instruction. the instruction is initi - ated by driving the cs# pin low and shift the instruction code "90h" followed by two dummy bytes and one bytes ad - dress (a7~a0). after which, the manufacturer id for macronix (c2h) and the device id are shifted out on the falling edge of sclk with most signifcant bit (msb) frst as shown in figure 26 . the device id values are listed in 7deohri ,''hqlwlrqv . if the one-byte address is initially set to 01h, then the device id will be read frst and then followed by the manufacturer id. the manufacturer and device ids can be read continuously, alternating from one to the other. the instruction is completed by driving cs# high. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
20 power-on state the device is at the states as below when power-up: - standby mode (please note it is not deep power-down mode) - w rite enable latch (wel) bit is reset the device must not be selected during power-up and power-down stage unless the vcc achieves below correct level (please refer to the fgure of "power-up timing ") : - vcc minimum at power- up stage and then after a delay of tvsl - gnd at power-down please note that a pull-up resistor on cs# may ensure a safe and proper power -up/down level. an internal power-on reset (por) circuit may protect the device from data corruption and inadvertent data change during power up state. for further protection on the device, if the vcc does not reach the vcc minimum level, the correct operation is not guaranteed. the read, write, erase, and program command should be sent after the time delay: tvsl after vcc reached vcc minimum level. please refer to the fgure of " power-up timing ". the device can accept read command after vcc reached vcc minimum and a time delay of tvsl. note: - to stabilize the vcc level, the vcc rail decoupled by a suitable capacitor close to package pins is recommend - ed.(generally around 0.1uf) p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
21 absolute maximum ratings electrical specifications capacitance ta = 25c, f = 1.0 mhz symbol parameter min. typ. max. unit conditions cin input capacitance 6 pf vin = 0v cout output capacitance 8 pf vout = 0v notice: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is stress rating only and functional operational sections of this specifcation is not implied. exposure to absolute maximum rating conditions for extended period may affect reliability. 2. specifcations contained within the following tables are subject to change. 3. during voltage transitions, all pins may overshoot to vcc+1.0v to vcc or -0.5v to gnd for period up to 20ns. rating value ambient operating temperature -40c to 85c storage temperature -65c to 150c applied input voltage -0.5v to vcc+0.5v applied output voltage -0.5v to vcc+0.5v vcc to ground potential -0.5v to vcc+0.5v figure 3. maximum negative overshoot waveform figure 4. maximum positive overshoot waveform 0v -0.5v 20ns 20ns 20ns vcc + 1.0v vcc 20ns 20ns 20ns p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
22 device under test cl 25k ohm 25k ohm +2.5v cl=30pf or 15pf including jig capacitance figure 5. input test waveforms and measurement level ac measurement level input timing reference level output timing reference level 0.8vcc 0.7vcc 0.3vcc 0.5vcc 0.2vcc note: input pulse rise and fall time are <5ns figure 6. output loading p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
23 symbol parameter notes min. typ. max. units test conditions ili input load current 1 2 ua vcc = vcc max vin = vcc or gnd ilo output leakage current 1 2 ua vcc = vcc max vout = vcc or gnd isb1 vcc standby current 1 15 25 ua vin = vcc or gnd cs#=vcc isb2 deep power-down current 2 10 ua vin = vcc or gnd cs#=vcc icc1 vcc read 1 12 ma f=75mhz ft=70mhz (dual output) sclk=0.1vcc/0.9vcc, so=open 10 ma f=66mhz sclk=0.1vcc/0.9vcc, so=open 4 ma f=33mhz sclk=0.1vcc/0.9vcc, so=open icc2 vcc program current (pp) 1 15 20 ma program in progress cs#=vcc icc3 vcc write status register (wrsr) current 3 15 ma program status register in progress cs#=vcc icc4 vcc sector erase current (se) 1 9 15 ma erase in progress cs#=vcc icc5 vcc chip erase current (ce) 1 15 20 ma erase in progress cs#=vcc vil input low voltage -0.5 0.3vcc v vih input high voltage 0.7vcc vcc+0.4 v vol output low voltage 0.4 v iol = 1.6ma voh output high voltage vcc-0.2 v ioh = -100ua vwi low vcc write inhibit voltage 3 1.5 2.3 v table 5. dc characteristics notes : 1. t ypical values at vcc = 3.3v, t = 25c. these currents are valid for all product versions (package and speeds). 2. typical value is calculated by simulation. 3. not 100% tested. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
24 table 6. ac characteristics symbol alt. parameter min. typ. max. unit fsclk fc clock frequency for the following instructions: fast_read, pp, se, be, ce, dp, res, rdp, wren, wrdi, rdid, rdsr, wrsr dc 75 mhz frsclk fr clock frequency for read instructions dc 33 mhz ftsclk ft clock frequency for dread instructions dc 70 mhz tch(1) tclh clock high time @33mhz 13 ns @75mhz 6 ns tcl(1) tcll clock low time @33mhz 13 ns @75mhz 6 ns tclch(2) clock rise time (3) (peak to peak) 0.1 v/ns tchcl(2) clock fall time (3) (peak to peak) 0.1 v/ns tslch tcss cs# active setup time (relative to sclk) 7 ns tchsl cs# not active hold time (relative to sclk) 7 ns tdvch tdsu data in setup time 2 ns tchdx tdh data in hold time 5 ns tchsh cs# active hold time (relative to sclk) 7 ns tshch cs# not active setup time (relative to sclk) 7 ns tshsl tcsh cs# deselect time read 15 ns write 40 ns tshqz(2) tdis output disable time 6 ns tclqv tv clock low to output valid 30pf 8 ns 15pf 6 ns tclqx tho output hold time 0 ns thlch hold# active setup time (relative to sclk) 5 ns tchhh hold# active hold time (relative to sclk) 5 ns thhch hold# not active setup time (relative to sclk) 5 ns tchhl hold# not active hold time (relative to sclk) 5 ns thhqx(2) tlz hold# to output low-z 6 ns thlqz(2) thz hold# to output high-z 6 ns twhsl(4) write protect setup time 20 ns tshwl(4) write protect hold time 100 ns tdp(2) cs# high to deep power-down mode 10 us tres1(2) cs# high to standby mode without electronic signature read 8.8 us tres2(2) cs# high to standby mode with electronic signature read 8.8 us tw write status register cycle time 5 40 ms tbp byte-program 9 50 us tpp page program cycle time 0.6 1 ms tse sector erase cycle time 40 200 ms tbe block erase cycle time 0.4 1 s tce chip erase cycle time 0.8 2 s notes: 1. tch + tcl must be greater than or equal to 1/f (fc or fr). 2. value guaranteed by characterization, not 100% tested in production. 3. expressed as a slew-rate. 4. only applicable as a constraint for a wrsr instruction when sr wd is set at 1. 5. test condition is shown as figure 5. 6. the cs# rising time needs to follow tclch spec and cs# falling time needs to follow tchcl spec. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
25 symbol parameter min. max. unit tvsl(1) vcc(min) to cs# low 200 us initial delivery state the device is delivered with the memory array erased: all bits are set to 1 (each byte contains ffh). the status register contains 00h (all status register bits are 0). note: 1. the parameter is characterized only. table 7. power-up timing p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
26 figure 7. serial input timing figure 8. output timing lsb addr.lsb in tshqz tch tcl tclqx tclqv tclqv sclk so cs# si sclk si cs# msb so tdvch high-z lsb tslch tchdx tchcl tclch tshch tshsl tchsh tchsl timing analysis p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
27 figure 9. hold timing * si is "don't care" during hold operation. figure 10. wp# disable setup and hold timing during wrsr when srwd=1 tchhl thlch thhch tchhh thhqx thlqz sclk so cs# hold# high-z 01 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 twhsl tshwl sclk si cs# wp# so p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
28 figure 11. write enable (wren) sequence (command 06) figure 12. write disable (wrdi) sequence (command 04) figure 13. read identifcation (rdid) sequence (command 9f) 21 34567 high-z 0 06 command sclk si cs# so 21 34567 high-z 0 04 command sclk si cs# so 21 3456789 10 11 12 13 14 15 command 0 manufacturer identification high-z msb 15 14 13 3210 device identification msb 7 6 5 3 2 1 0 16 17 18 28 29 30 31 sclk si cs# so 9f p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
29 figure 14. read status register (rdsr) sequence (command 05) figure 15. write status register (wrsr) sequence (command 01) figure 16. read data bytes (read) sequence (command 03) 21 3456789 10 11 12 13 14 15 command 0 7 6543210 status register out high-z msb 7 6543210 status register out msb 7 sclk si cs# so 05 21 345678 9 10 11 12 13 14 15 status register in 0 76543 2 0 1 msb sclk si cs# so 01 high-z command sclk si cs# so 23 21 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 76543 1 7 0 data out 1 24-bit address 0 msb msb 2 39 data out 2 03 high-z command p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
30 figure 17. read at higher speed (fast_read) sequence (command 0b) 23 21 3456789 10 28 29 30 31 22 21 3210 high-z 24 bit address 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 765432 0 1 data out 1 dummy byte msb 7 6543210 data out 2 msb msb 7 47 765432 0 1 35 sclk si cs# so sclk si cs# so 0b command figure 18. dual output read mode sequence (command 3b) high impedance 21 345678 0 sclk si/so0 so/so1 cs# 9 10 11 30 31 32 3b(hex) dummy address bit23, bit22, bit21...bit0 data bit6, bit4, bit2...bit0, bit6, bit4.... data bit7, bit5, bit3...bit1, bit7, bit5.... 39 40 41 42 43 8 bit instruction 24 bit address 8 dummy cycle data output p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
31 figure 19. page program (pp) sequence (command 02) 4241 43 44 45 46 47 48 49 50 52 53 54 55 40 23 21 345678 9 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 24-bit address 0 76543 2 0 1 data byte 1 39 51 76543 2 0 1 data byte 2 76543 2 0 1 data byte 3 data byte 256 2079 2078 2077 2076 2075 2074 2073 76543 2 0 1 2072 msb msb msb msb msb sclk cs# si sclk cs# si 02 command p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
32 figure 20. sector erase (se) sequence (command 20) note: se command is 20(hex). figure 21. block erase (be) sequence (command 52 or d8) note: be command is 52 or d8(hex). 24 bit address 21 3456789 29 30 31 0 23 22 2 1 0 msb sclk cs# si 20 command 24 bit address 21 3456789 29 30 31 0 23 22 2 0 1 msb sclk cs# si 52 or d8 command p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
33 figure 22. chip erase (ce) sequence (command 60 or c7) figure 23. deep power-down (dp) sequence (command b9) figure 24. read electronic signature (res) sequence (command ab) note: ce command is 60(hex) or c7(hex). 21 34567 0 60 or c7 sclk si cs# command 21 34567 0 t dp deep power-down mode stand-by mode sclk cs# si b9 command 23 21 3456789 10 28 29 30 31 32 33 34 35 22 21 3210 36 37 38 765432 0 1 high-z electronic signature out 3 dummy bytes 0 msb stand-by mode deep power-down mode msb t res2 sclk cs# si so ab command p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
34 figure 25. release from deep power-down (rdp) sequence (command ab) figure 26. read electronic manufacturer & device id (rems) sequence (command 90) notes: (1) add=00h will output the manufacturer's id frst and add=01h will output device id frst 21 34567 0 t res1 stand-by mode deep power-down mode high-z sclk cs# si so ab command 15 14 13 3 2 1 0 21 345678 9 10 2 dummy bytes 0 32 33 34 36 37 38 39 40 41 42 43 44 45 46 76543 2 0 1 manufacturer id add (1) msb 7 6543210 device id msb msb 7 47 76543 2 0 1 35 31302928 sclk si cs# so sclk si cs# so x 90 high-z command p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
35 figure 27. power-up timing v cc v cc (min) chip selection is not allowed tvsl time device is fully accessible v cc (max) p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
36 recommended operating conditions at device power-up ac timing illustrated in figure 2 8 and figure 2 9 are for the supply voltages and the control signals at device power- up and power-down. if the timing in the fgures is ignored, the device will not operate correctly . during power-up and power-down, cs# needs to follow the voltage applied on vcc to keep the device not to be selected. the cs# can be driven low when vcc reach vcc(min.) and wait a period of tvsl. notes : 1. sampled, not 100% tested . 2. for ac spec tchsl, tslch, tdvch, tchdx, tshsl, tchsh, tshch, tchcl, tclch in the fgure, please refer to "ac characteristics" table. symbol parameter notes min. max. unit tvr vcc rise time 1 20 500000 us/v figure 28. ac timing at device power-up sclk si cs# vcc msb in so tdvch high impedance lsb in tslch tchdx tchcl tclch tshch tshsl tchsh tchsl tvr vcc(min) gnd p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
37 figure 29. power-down sequence cs# sclk vcc during power-down, cs# needs to follow the voltage drop on vcc to avoid mis-operation. p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
38 erase and programming performance parameter min. typ. (1) max. (2) unit write status register cycle time 5 40 ms sector erase time 40 200 ms block erase time 0.4 1 s chip erase time 0.8 2 s byte program time (via page program command) 9 50 us page program time 0.6 1 ms erase/program cycle 100,000 cycles notes: 1. t ypical program and erase time assumes the following conditions: 25c, 2.5v, and checker board pattern. 2. under worst conditions of 85c and 2.35v . 3. system-level overhead is the time required to execute the frst-bus-cycle sequence for the programming com - mand. 4. erase/program cycles comply with jedec: jesd47 & jesd22-a117 standard. min. max. input voltage with respect to gnd on all power pins, si, cs# -1.0v 2 vccmax input voltage with respect to gnd on so -1.0v vcc + 1.0v current -100ma +100ma includes all pins except vcc. test conditions: vcc = 2.5v, one pin at a time. latch-up characteristics data retention parameter condition min. max. unit data retention 55?c 20 years p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
39 part no. clock (mhz) temperature package remark MX25V1006Ezui-13g 75 -40 to 85c 8-uson (2x3mm) MX25V1006Eoi-13g 75 -40 to 85c 8-tssop (173mil) MX25V1006Emi-13g 75 -40 to 85c 8-sop (150mil) ordering information p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
40 part name description mx 25 v 13 zu i g option: g: rohs compliant and halogen-free speed: 13: 75mhz temperature range: i: industrial (-40c to 85c) package: zu: 2x3mm 8-uson o: 173mil 8-tssop m: 150mil 8-sop density & mode: 1006e: 1mb type: v: 2.5v device: 25: serial flash 1006e p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
41 package information p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
42 p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
43 p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
44 revision history revision no. description page date 1.0 1. removed "advanced information" p4 oct/28/201 1 1.1 1. added 150mil 8-sop package solution p5,6,39, ma y/16/2013 p40,43 1.2 1. removed "advanced information" status of MX25V1006Emi-13g p39 jun/17/2013 1.3 1. updated pa rameters for dc/ac characteristics p4,23,24 nov/12/2013 2. updated erase and programming performance p4,38 p/n: pm1752 rev. 1.3, nov. 12, 2013 MX25V1006E http://
MX25V1006E 45 macronix international co., ltd. reserves the right to change product and specifcations without notice. except for customized products which has been expressly identifed in the applicable agreement, macronix's products are designed, developed, and/or manufactured for ordinary business, industrial, personal, and/or household applications only, and not for use in any applications which may, directly or indirectly, cause death, personal injury, or severe property damages. in the event macronix products are used in contradicted to their target usage above, the buyer shall take any and all actions to ensure said macronix's product qualifed for its actual use in accordance with the applicable laws and regulations; and macronix as well as its suppliers and/or distributors shall be released from any and all liability arisen therefrom. copyright? macronix international co., ltd. 2011~2013. all rights reserved, including the trademarks and tradename thereof, such as macronix, mxic, mxic logo, mx logo, integrated solutions provider, nbit, nbit, nbiit, macronix nbit, eliteflash, hybridnvm, hybridflash, xtrarom, phines, kh logo, be-sonos, ksmc, kingtech, mxsmio, macronix vee, macronix map, rich au dio, rich book, rich tv, and fitcam. the names and brands of third party referred thereto (if any) are for identifcation purposes only . for the contact and order information, please visit macronixs web site at: http://www.macronix.com http://

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